Layout Design Staff Engineer

Responsibilities

• Lead physical layout design for advanced memory IP including SRAM, ROM, and eDRAM at the cell, array, and peripheral circuit levels
• Ensure layouts meet foundry process design rules and memory-specific constraints, resolving DRC and LVS issues
• Optimize layouts for area efficiency, performance targets, power consumption, yield improvement, and manufacturability
• Perform RC extraction and parasitic analysis on dense memory arrays to improve signal integrity and timing margins
• Debug complex layout issues including electromigration, IR drop, and soft error susceptibility
• Collaborate with circuit designers, verification engineers, and process teams to deliver first-pass silicon success
• Mentor junior layout engineers on best practices, tool usage, and design tradeoffs

Requirements

• Bachelor's or Master's degree in Electronics Engineering, Telecommunication, Physics, or a related technical field
• At least 5 years of hands-on experience in custom layout design with a focus on memory structures (SRAM, ROM, or eDRAM)
• Deep expertise in memory layout at the transistor and cell level, including array structures and peripheral circuits
• Proficiency with layout tools such as Custom Compiler, Virtuoso, or IC Compiler
• Strong working knowledge of foundry process design rules and DRC/LVS verification flows
• Experience performing RC extraction and analyzing parasitic effects

Benefits

• Comprehensive medical and healthcare plans
• Paid time away including company holidays and ETO/FTO programs
• Family support including maternity/paternity leave and adoption assistance
• Employee Stock Purchase Plan (ESPP) with a 15% discount
• Competitive salaries and regional retirement plans

About the Company

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation, and analysis solutions to power innovation across various industries.