Layout Design, Sr Engineer

Responsibilities

• Design and integrate memory leafcell and standard cell layouts using Custom Compiler, optimizing for area, speed, and power across advanced FinFET technology nodes
• Run and debug physical verification flows including DRC, LVS, ERC, and antenna checks using ICV or similar platforms to achieve tapeout-ready results
• Collaborate with circuit designers and verification engineers to ensure layout matches design intent and meets performance targets
• Build layout automation scripts in Perl, Shell, or TCL to accelerate repetitive tasks and improve consistency across design variants
• Optimize existing layouts for density and performance, identifying opportunities to shrink area or reduce parasitics

Requirements

• 2+ years of hands-on experience in custom layout, standard cell layout, or memory layout design
• Deep familiarity with FinFET technology nodes and associated design rules
• Proficiency with Custom Compiler and physical verification tools (ICV, Calibre, etc.)
• Strong skills in DRC, LVS, and ERC debugging within hierarchical designs
• Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, or a related field
• Experience writing layout automation scripts in Perl, Shell, or TCL

Benefits

• Comprehensive medical and healthcare plans
• Paid time away including ETO and FTO programs
• Family support including maternity/paternity leave and adoption assistance
• Employee Stock Purchase Plan (ESPP) with a 15% discount
• Competitive salaries and regional retirement plans

About the Company

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation, and analysis solutions, partnering closely with customers across various industries to maximize R&D productivity.