IP RTL Design Engineer

Responsibilities

• Write, verify, and maintain synthesizable RTL for LPDDR PHY blocks
• Write SDC constraints, perform synthesis, and ensure timing closure
• Setup and run IPXACT, LINT, CDC, SDC, PreSTA, DFT, and ATPG checks
• Support silicon validation bring-up and debug post-silicon issues
• Collaborate with internal and external customers to meet requirements and delivery timelines

Requirements

• 4+ years of full-cycle RTL/logic design experience, preferably in memory-PHY or high-speed interface IP
• Strong RTL coding proficiency in Verilog or SystemVerilog
• Experience with QC tools including LINT, CDC, DFT, and ATPG
• Proficiency in SDC creation, Synthesis, and STA
• B.Tech, B.E, M.Tech, or M.E degree

Preferred Qualifications

• Prior professional work on LPDDR or HBM PHY projects

About the Company

Samsung Semiconductor India Research (SSIR) is a major R&D center for Samsung Electronics, focusing on cutting-edge semiconductor solutions including System LSI, Memory, and Foundry technologies. Our engineers work on diverse, high-impact domains such as AI/ML, 5G/6G, Mobile SoCs, and high-performance Memory PHY IP.