Infra Design Verification Sr Lead Engineer

Responsibilities

• Develop and maintain UVM-based verification environments for high-speed interconnect protocols including PCIe, CXL, and AXI.
• Create and execute comprehensive verification plans for PCIe, CXL, AXI, and CHI protocols.
• Perform block-level and top-level verification, including functional coverage, assertion-based verification, and regression testing.
• Collaborate with RTL designers, architects, and validation teams to ensure design correctness and coverage closure.
• Implement and enhance scoreboards, agents, monitors, and sequences.
• Integrate and validate SMMU and Coresight components in subsystem environments.
• Debug failures at both RTL and gate-level simulations.
• Mentor junior engineers and contribute to continuous improvements in verification methodology.

Requirements

• Bachelor's degree in Computer Science, Electrical/Electronics Engineering, or a related field.
• 3+ years of Hardware Engineering experience (or 2+ years with a Master's, or 1+ year with a PhD).
• Strong proficiency in SystemVerilog, UVM, and modern verification methodologies.
• Deep understanding of PCIe (Gen3/4/5/6), CXL (1.1/2.0/3.0), and AXI/CHI protocols.
• Expertise in assertion-based verification (SVA) and coverage-driven testing.
• Proficiency in scripting languages such as Python, Perl, or Tcl for automation.
• Familiarity with Synopsys or Mentor VIPs for protocol compliance and simulation.

Preferred Qualifications

• 6–10+ years of ASIC, Subsystem, or SoC verification experience.
• Experience with USB, Ethernet, or other peripheral protocols.
• Exposure to post-silicon validation and lab bring-up.
• Knowledge of power-aware verification (UPF) and formal verification.

About the Company

Qualcomm is a leading technology innovator that pushes the boundaries of what's possible to enable next-generation experiences and drive digital transformation for a smarter, connected future.