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Posted a day ago
IC Package Engineer
EtchedIC Package Engineer
Perks & benefits
Medical InsuranceHousing AllowanceRelocation AllowanceCommissionPaid LeaveHealth InsuranceVisa
Requirements
Bachelor's or Master's in EE or ME, 5+ years advanced IC package design experience, Expertise in CoWoS and BGA design, Proficiency in Cadence APD/SIP or Mentor Xpedition
Skills
CAD
About the role
About the Company
Etched is building AI chips that are hard-coded for individual model architectures. Our first product (Sohu) only supports transformers, but has an order of magnitude more throughput and lower latency than a B200. With Etched ASICs, you can build products that would be impossible with GPUs.
Responsibilities
- Own the end-to-end package design process, including substrate layout and IC package design
- Leverage advanced packaging technologies like CoWoS and heterogeneous integration
- Manage large-scale BGA design for packages exceeding 4000-ball arrays
- Conduct mechanical and warpage analysis to address coplanarity requirements
- Perform design validation against electrical and mechanical constraints
- Collaborate cross-functionally with chip design, thermal, mechanical, and manufacturing teams
- Oversee package reliability testing including thermal, warpage, shock, and electrical tests
Requirements
- Bachelor’s or Master’s degree in Electrical Engineering, Mechanical Engineering, or related discipline
- 5+ years of experience in advanced IC package design (CoWoS or equivalent)
- Experience in substrate layout and BGA package design for large ball arrays (>4000 balls)
- Proficiency in package design tools such as Cadence APD/SIP or Mentor Xpedition
- Familiarity with mechanical stress analysis and simulation methodologies
- Experience with advanced packaging nodes (2.5D/3D stacking)
- Knowledge of thermal management techniques in package design
Preferred Qualifications
- Previous experience working in AI, HPC, or semiconductor design companies
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Etched · Cupertino
