HW SOC/ASIC Physical Design Engineer, Senior

Responsibilities

• Execute floorplanning, placement, clock tree synthesis (CTS), and routing using industry-standard tools such as Innovus or ICC2.
• Drive timing closure across multiple corners and modes using static timing analysis (STA) tools like PrimeTime.
• Architect and implement robust, low-skew, power-efficient clock distribution networks.
• Collaborate with RTL designers to resolve timing, congestion, and DRC issues.
• Optimize designs for power, performance, and area (PPA) using CLP methodology.
• Perform full-chip and block-level physical verification, including DRC, LVS, ERC, and antenna checks.
• Develop and maintain automation scripts in TCL, Python, or Perl for reference flow automation.
• Support signoff verification, including multi-corner/multi-mode analysis and ECO validation.

Requirements

• US Citizenship is required.
• Bachelor's degree in Science, Engineering, or a related field.
• 2+ years of ASIC design, verification, validation, or integration experience.
• Hands-on experience with RTL-to-GDSII flow.
• Proficiency with EDA tools for CTS, STA, and physical verification (e.g., Innovus, ICC2, PrimeTime).
• Strong scripting skills in TCL, Python, or Perl.
• Solid understanding of digital timing concepts, clock domain crossing, and synchronous/asynchronous design.

Preferred Qualifications

• Experience with advanced nodes (e.g., 7nm, 5nm, 3nm) and FinFET technologies.
• Experience with custom clock tree architectures such as H-tree, mesh, or spine-based topologies.
• Knowledge of EM/IR analysis, thermal-aware clocking, and reliability modeling.
• Exposure to high-speed interface clocking such as SerDes, DDR, or PCIe.

About the Company

Qualcomm is a global leader in wireless technology, developing breakthrough innovations that impact lives around the world. We foster a supportive, inclusive culture where the brightest minds work together to solve the most complex challenges in semiconductor and wireless engineering.