High Speed Interface (IO) Design Engineer

Responsibilities

• Integrate and verify HSI IP blocks in SoC and support physical implementation
• Configure HSI IP blocks to be integrated into SoC to achieve maximum performance
• Perform performance analysis in chip top level (bus, memory bandwidth) simulation and FPGA prototyping
• Test, debug, and troubleshoot silicon in collaboration with HSI IP vendors

Requirements

• 5+ years of industry experience in chip design specializing in HSI technology
• Experience in RTL design and logic synthesis
• Experience in verification and timing closure

Preferred Qualifications

• Excellent understanding of High-Speed Interface standard specifications (e.g., PCIe, LPDDR, HBM, Ethernet, or D2D)
• High understanding of High-Speed interface technology such as SERDES, Channel encoding, OSI-7 layer, and Equalization
• Experience in SoC design with HSI and troubleshooting in Silicon using Test Equipment
• Understanding of system-level usage of HSI applications