High Level Synthesis Compiler Engineer

Responsibilities

• Develop and optimize the compiler for FPGA design flows, including IR, lowering, analysis, and transformation passes
• Implement correctness- and QoR-driven optimizations and ensure scalability for large designs
• Work closely with customers to understand target applications and translate their needs into concrete compiler and flow improvements
• Mentor talented engineers through code reviews, design reviews, and technical coaching
• Document behavior, limitations, and workarounds for both internal and external audiences
• Stay current with EDA and compiler technology, including LLVM/MLIR ecosystems and FPGA design practices

Requirements

• Bachelor's or Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field
• 8+ years of professional experience building compilers, LLVM/MLIR-based tools, or EDA/FPGA implementation software
• Strong C++ skills for production systems, including performance, multi-threading, and large codebases
• Hands-on experience with MLIR and/or LLVM (IR design, passes, backends, or integration)
• Solid digital design and FPGA background, including LUT/FF/BRAM/DSP primitives and timing
• Familiarity with FPGA or ASIC implementation flows such as synthesis, place-and-route, and STA
• Proven ability to mentor other engineers and collaborate effectively with customers

Preferred Qualifications

• PhD in Electrical Engineering, Computer Engineering, or Computer Science
• Exposure to simulation, formal, or debug environments, or high-level design flows (HLS)
• Experience shipping software used by external customers or large internal user bases

About the Company

Altera provides leadership programmable solutions that are easy-to-use and deploy in applications from cloud to edge, offering limitless AI possibilities. Our end-to-end broad portfolio of products includes FPGAs, CPLDs, Intellectual Property, development tools, System on Modules, SmartNICs, and IPUs.