HBM SoC Physical Design Engineer

Responsibilities

• Own physical implementation for SoC blocks and top-level, including floor-planning, placement, CTS, routing, and physical optimization to meet PPA targets.
• Drive timing closure (setup/hold) across multi-mode/multi-corner (MMMC) scenarios.
• Integrate complex IP such as controllers, microcontrollers, NOC, and MBIST/DFT logic.
• Perform physical signoff, including DRC/LVS, IR drop/EM, and timing signoff.
• Partner with DFT, packaging, and manufacturing teams to ensure manufacturability and quality.
• Support tape-out execution and contribute to post-silicon debug.
• Improve productivity through scripting, automation, and methodology development.

Requirements

• Strong experience in SoC physical design implementation from netlist to GDSII on advanced nodes.
• Proficiency with industry EDA tools such as Cadence Innovus/Tempus, Synopsys ICC2/PrimeTime, or Siemens Calibre.
• Solid understanding of STA fundamentals, clocking, and constraints (SDC).
• Experience with power intent and power delivery (UPF/CPF concepts).
• Familiarity with physical verification/signoff concepts including DRC, LVS, and ERC.

Preferred Qualifications

• Experience with HBM/DRAM adjacent SoC designs or memory-subsystem-heavy SoCs.
• Bachelor’s or master’s degree in Electrical Engineering, Computer Engineering, or a related field.
• Minimum 10 years of experience in a related field.
• Proven ability to mentor and develop junior engineers.

Benefits

• Choice of medical, dental, and vision plans.
• Income protection programs for illness or injury.
• Paid family leave.
• Robust paid time-off program and paid holidays.

About the Company

Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.