Hardware Validation and Debug Engineer - DDR

About the Company

Graphcore is a globally recognised leader in Artificial Intelligence computing systems. The company designs advanced semiconductors and data centre hardware that provide the specialised processing power needed to drive AI innovation.

Responsibilities

• Perform Validation and Debug for new hardware platforms
• Debug PCB, power, signal integrity, and interface issues
• Validate and debug high-speed memory interfaces (LPDDR5-9600) and slow speed interfaces (SPI/I2C/I3C/UART)
• Support LPDDR5-9600 initialization, training, timing optimization, margin analysis, and stability validation
• Analyse DDR timing margins, signal integrity, eye diagrams, and training behaviour
• Identify root causes and drive corrective actions across hardware and firmware domains
• Create bring-up documentation, test procedures, and debug reports

Requirements

• Hardware Debug expertise
• LPDDR validation and tuning experience
• Signal integrity analysis skills
• DDR training and margin analysis
• Protocol-level debugging and root-cause analysis
• Low-level system integration experience
• Proficiency with high-bandwidth oscilloscopes, BERT systems, and VNA/TDR equipment
• Hands-on experience with LPDDR5 memory subsystems and compliance testing

Preferred Qualifications

• Knowledge of PCBA and system level technologies
• Ethernet and PCIe validation experience
• Background knowledge of ATE systems
• Ability to script automation and data analysis using Python, LabView, or BASH