Front-End Power Engineer

Responsibilities

• Optimize RTL designs to boost power efficiency while meeting performance and area objectives
• Perform power analysis throughout silicon design stages, applying clock gating, power gating, multi-voltage domains, and dynamic voltage scaling
• Conduct power estimation and evaluate PPA trade-offs for new and existing design features
• Collaborate closely with the physical design team to ensure power targets are met during synthesis, place-and-route, and sign-off
• Create precise power models from RTL simulations and gate-level netlists, and perform power roll-up analysis to estimate chip-level power consumption

Requirements

• Experience in RTL development using Verilog/SystemVerilog
• Focus on low-power RTL design and optimization for complex digital systems
• In-depth knowledge of low-power techniques like clock gating, power gating, and dynamic voltage/frequency scaling (DVFS)
• Familiarity with synthesis and place-and-route processes with an emphasis on optimizing for power

Preferred Qualifications

• UPF/CPF power intent specifications
• Power analysis tools such as Synopsys PrimePower, Cadence Joules, or similar
• Automation of power analysis and optimization workflows using scripting languages (Tcl, Perl, Python)

Benefits

• Full medical, dental, and vision packages with 100% of premium covered
• Housing subsidy of $2,000/month for those living within walking distance of the office
• Daily lunch and dinner in the office
• Relocation support for those moving to Cupertino

About the Company

Etched builds AI chips that are hard-coded for individual model architectures. Its first product, Sohu, supports transformers with an order of magnitude more throughput and lower latency than a B200. The company is a fully in-person team based in Cupertino.