FPGA SW Validation Engineer

Responsibilities

• Validate and research compiler optimizations, Partial Reconfiguration (PR) flows, and debugging features such as SignalTap and System Console.
• Create designs using HDLs and Altera IPs and verify functionality and timing on Altera FPGA hardware boards.
• Perform design regressions during each release to monitor Quality of Results (QoR) and assess performance improvements on targeted FPGA devkits.
• Collaborate with cross-functional teams to develop improved validation strategies and resolve customer issues.

Requirements

• 5+ years of experience in FPGA/ASIC Design, RTL Coding, Verification, and Hardware Debugging.
• Proficiency in RTL design and verification using VHDL, Verilog, or SystemVerilog.
• Hands-on experience with FPGA devices (Agilex, Virtex) and tools (Altera Quartus, Xilinx Vivado, or Synplify).
• Strong experience with FPGA Partial Reconfiguration (PR) flows and hardware debugging using SignalTap or ChipScope.
• Experience with simulation and verification tools such as VCS, Questa, or XCelium.
• Proficiency in Unix/Linux environments with automation scripting in Shell, Perl, TCL, or Python.
• Solid understanding of protocols including PCIe, Ethernet, Avalon, AHB, AXI, HPS, and high-speed interfaces.
• Bachelor's or Master's degree in Electronics, VLSI, Digital Design, or a related field.

About the Company

Altera provides leadership programmable solutions that are easy-to-use and deploy in applications from cloud to edge, offering limitless AI possibilities. Our end-to-end broad portfolio of products, including FPGAs, CPLDs, Intellectual Property, and development tools, provides the flexibility to accelerate innovation and shape the future through pioneering technology.