FPGA Prototyping Applications Engineer

Responsibilities

• Validate new features in Synplify FPGA synthesis, ProtoCompiler, and Zebu tools from a customer perspective
• Analyze quality of results across synthesis runs and propose recommendations to improve timing, area, and power outcomes
• Write Verilog and VHDL test benches to exercise edge cases and stress tool limits
• Author technical application notes and SolvNet articles to assist customers with feature usage and troubleshooting
• Work closely with R&D teams to translate validation results into actionable product improvements
• Debug synthesis, back-end flow, and FPGA architecture issues surfacing during validation or customer escalations

Requirements

• Bachelor's or Master's degree in Electronics Engineering, Computer Engineering, or a related field
• 5+ years of hands-on experience in logic design and FPGA implementation (RTL through hardware bring-up)
• Proficiency in Verilog and VHDL
• Solid experience with synthesis tools, back-end FPGA flows, and FPGA architecture
• Strong understanding of verification concepts and writing effective test benches

Preferred Qualifications

• Experience with Xilinx or Altera synthesis software
• Scripting ability in Python, Tcl, or Perl for automating validation and analysis tasks

About the Company

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services to maximize R&D capability and productivity.