FPGA Engineer

Responsibilities

• Design, architect, and develop FPGA RTL (VHDL/Verilog) for high-speed serial protocols
• Handle complex FPGA design challenges including CDC, multi-clock domains, timing closure, and SerDes optimization
• Perform synthesis, place-and-route, and timing optimization using Xilinx Vivado
• Debug and validate FPGA designs and board-level high-speed interfaces
• Collaborate with global engineering teams for end-to-end FPGA solution delivery
• Utilize AI-assisted development tools to enhance RTL productivity

Requirements

• 7+ years of hands-on FPGA design and development experience
• Strong expertise in high-speed serial protocols (PCIe, NVMe, CXL, Ethernet, USB, etc.)
• Expertise in CDC handling, multi-clock domain design, and timing closure
• Hands-on experience with Xilinx Vivado and simulation tools (ModelSim, Questa, VCS)
• Bachelor’s or Master’s degree in Electrical/Electronics Engineering

Preferred Qualifications

• Degree from Tier-1 institutes such as IITs or NITs
• Experience working in global or cross-functional R&D teams