FPGA Development Tools Engineer – Synthesis

Responsibilities

• Design, implement, and optimize synthesis algorithms to convert RTL into efficient gate-level representations
• Contribute to the FPGA compiler toolchain, integrating synthesis with placement, routing, and timing stages
• Improve Quality of Results (QoR) by optimizing performance, power, and area (PPA)
• Develop tools and methodologies for analyzing and transforming complex RTL designs
• Collaborate with architecture, STA, placement, and routing teams to ensure toolchain alignment
• Debug synthesis results, including timing and logic structure issues
• Develop internal tools, scripting, and automation to improve synthesis flows

Requirements

• 6+ years of experience in FPGA/ASIC design, EDA tools, or related fields
• Strong hands-on experience with Verilog, SystemVerilog, or VHDL
• Proficiency in C/C++ for tool development
• Strong understanding of algorithms and data structures
• Knowledge of logic synthesis, optimization techniques, and FPGA/ASIC design flows
• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field

Preferred Qualifications

• Experience with synthesis tools or FPGA toolchains such as Quartus or Vivado
• Knowledge of FPGA architectures including LUTs, DSPs, BRAM, and interconnect
• Familiarity with advanced optimizations like retiming, logic restructuring, and resource sharing
• Scripting experience in Python or Tcl
• Background in compiler development or EDA algorithms

About the Company

Altera provides leadership programmable solutions that are easy-to-use and deploy in applications from cloud to edge, offering limitless AI possibilities. Our broad portfolio includes FPGAs, CPLDs, Intellectual Property, development tools, and System on Modules to help accelerate innovation.