FPGA Design Engineer

Responsibilities

• Lead the selection, procurement, and bring-up of FPGA prototyping platforms for pre-silicon RTL validation and software development
• Adapt and implement complex ASIC RTL onto FPGA targets, including multi-clock-domain architectures and timing closure
• Integrate in-house designs with third-party and vendor IP within the AMD/Xilinx ecosystem
• Design, implement, and validate high-speed I/O with a focus on PCIe
• Build FPGA-based tester designs for silicon bring-up, device characterization, and automated test environments
• Develop the software layer including Python/C++ hardware abstraction and register-map generation
• Root-cause complex timing and functional issues using ILA/Vivado Analyzer, oscilloscopes, and logic analyzers

Requirements

• Proven industry experience taking FPGA designs from RTL through timing closure to validated hardware
• Expert-level SystemVerilog and/or VHDL for synthesis
• Deep proficiency in Xilinx Vivado (synthesis, place & route, timing closure, IP catalog)
• Hands-on experience implementing and debugging PCIe, AXI/AHB, SPI, UART, and JTAG
• Strong Python skills for automation, test, and build tooling
• Strong board-level bring-up and lab debugging skills on real hardware
• Startup mindset with ability to work independently on ambiguous problems

Preferred Qualifications

• Experience with verification frameworks like Cocotb, UVM, or OSVVM
• Experience deploying ML models to FPGAs (hls4ml, FINN, or custom NN-to-RTL flows)
• Mixed-signal ASIC exposure including digital front-ends or ADC/DAC interfaces
• SERDES tuning and signal integrity fundamentals
• CI/CD for hardware using GitLab CI or Docker

About the Company

Normal Computing builds silicon that turns thermal noise from an obstacle into a computational resource. We co-design the full stack, from AI-native EDA systems to advanced ASICs, providing 10-100× more AI inference per dollar and watt.