Formal Verification Engineer, Staff

Responsibilities

• Drive formal verification of complex design blocks using advanced Formal Apps and robust convergence strategies.
• Collaborate with global architecture, design, and systems teams to achieve verification goals.
• Review and refine formal setups, proofs, constraints, and abstractions with design and DV teams.
• Engage with EDA vendors to evaluate advanced DV methodologies and improve sign-off quality.
• Develop automation scripts, preferably in Python, to enhance the efficiency and scalability of FV flows.
• Analyze challenging formal problems and propose effective verification strategies.
• Implement low power formal methodologies.

Requirements

• 6+ years of hands-on experience in Formal Verification.
• Strong understanding of formal concepts, proof strategies, and abstraction techniques.
• Proficiency with formal tools such as Jasper, VC Formal, or Questa Formal.
• Working knowledge of property-based FV (SVA).
• Excellent scripting skills, with a strong preference for Python.
• Strong analytical and problem-solving abilities.
• Bachelor's degree in Computer Science, Electrical/Electronics Engineering, or a related field (with relevant experience) or higher.

Preferred Qualifications

• Knowledge of low-power verification concepts (e.g., UPF/CPF, isolation/retention, power/clock gating).
• Experience with power-aware verification apps and power-intent debugging.

About the Company

Qualcomm is a global leader in wireless technology, developing breakthrough innovations that impact lives around the world. We foster a supportive, inclusive culture where the brightest minds collaborate to solve the most complex challenges in engineering and technology.