Formal Verification Engineer

About the Company

Etched is building hardware for frontier intelligence. We co-design chips, racks, software, and manufacturing to deliver best-in-class throughput and latency across both prefill and decode workloads. Our first products are heavily focused on inference.

Responsibilities

• Define and drive formal verification strategy across the ASIC DV team for complex IP blocks and SoC integration logic
• Develop formal verification plans covering functional correctness, connectivity, ordering, and deadlock/livelock freedom
• Build reusable formal environments using SystemVerilog Assertions, assumptions, constraints, and checkers
• Drive proof convergence using abstractions, cut-points, and assume-guarantee reasoning
• Work with architects and RTL designers to translate design intent into high-value formal properties
• Partner with UVM DV, emulation, software, and firmware teams to align formal verification with simulation and coverage
• Debug complex RTL, protocol, datapath, and connectivity bugs using formal counterexamples and waveforms
• Contribute to formal sign-off methodology, regression automation, and design-for-formal best practices

Requirements

• 5+ years of design verification experience with significant hands-on formal verification experience
• Strong proficiency with SystemVerilog and SystemVerilog Assertions (SVA)
• Experience with commercial formal tools such as Cadence JasperGold, Synopsys VC Formal, or Siemens Questa Formal
• Strong understanding of digital design, computer architecture, datapaths, and SoC interfaces
• Ability to model complex design behavior using assumptions, abstractions, and constraints
• Strong debugging skills across RTL, specifications, and formal counterexamples
• Experience collaborating across architecture, RTL design, UVM DV, and software teams

Preferred Qualifications

• Experience with formal verification of systolic arrays, DMA engines, NoCs, or memory subsystems
• Knowledge of PCIe, Ethernet, AXI/AMBA, or CPU interfaces
• Experience with protocol compliance checking, connectivity checking, or register verification
• Scripting skills in Python, TCL, or Perl for automation and regression management