Fellow - FPGA Architecture

Responsibilities

• Own FPGA configuration architecture, including bitstream, boot flows, interfaces, compression, security, and reliability
• Define next-generation Partial Reconfiguration architecture for low-latency, secure dynamic updates
• Drive innovation in runtime reconfiguration for high-availability and adaptive systems
• Architect readback, debug, and observability infrastructure for validation and in-field diagnostics
• Define configuration security, including secure boot, key management, and update flows
• Drive system trade-offs across configuration bandwidth, latency, and power
• Develop clear architecture specifications for configuration, PR, and debug subsystems
• Align with software/tools teams for end-to-end configuration and PR flows
• Collaborate with silicon and design teams for scalable high-quality implementation
• Mentor architects and elevate FPGA architecture standards across the organization

Requirements

• BS, MS, or PhD in Electrical/Computer Engineering or a related field
• Deep expertise in FPGA configuration and Partial Reconfiguration
• Strong understanding of bitstream architecture, protocols, boot flows, and security
• Experience in ASIC/SoC design and integration with hardened subsystems
• Proven track record as a technical leader in FPGA systems or architecture

Preferred Qualifications

• Experience with readback/debug infrastructure and field diagnostics
• Familiarity with FPGA toolchains including synthesis, P&R, and PR flows
• Ability to define architecture across silicon, tools, and software layers
• Significant architectural contributions, such as patents or industry publications

About the Company

AMD's mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we push the limits of innovation to solve the world’s most important challenges.