DV Formal Verification

Responsibilities

• Own block- and SOC-level formal verification, debug, and proof convergence for AI accelerator silicon
• Use and develop AI-assisted tool flows, including AI agents for proof guidance, to accelerate convergence on complex designs
• Collaborate with chip-design and software teams from first silicon through scale-out

Requirements

• Master's degree with 8+ years of experience in block- and full-chip formal verification on complex SOCs
• Exceptional abilities in property authoring (SVA / PSL), proof strategies, and tool-flow ownership
• Demonstrated ability to debug proof failures and drive convergence with RTL designers and architects
• Hands-on experience with industry-standard formal tools such as Synopsys VC Formal, Cadence Jasper, or equivalent

Preferred Qualifications

• Experience in security verification or processor verification
• Experience with equivalence checking or AMS / IP-flow exposure

Benefits

• Equity grant per company guidelines
• Medical, dental, and vision insurance
• 401(k)
• Standard PTO
• Visa sponsorship support (H-1B, O-1, TN, E-3, etc.)

About the Company

DensityAI is developing advanced AI accelerator silicon, driving programs from first silicon through scale-out.