DSP/NPU Design Verification Sr Engineer

Responsibilities

• Drive design verification of complex proprietary DSP/NPU IP by working with global design, architecture, and implementation teams.
• Implement and improve SystemVerilog/UVM testbench architectures.
• Develop and deploy new verification methodologies and automation to improve quality and efficiency.
• Create design-corresponding test plans, architect verification environments, and meet coverage goals.
• Perform hands-on simulations and debug failures at the IP, Subsystem, and SoC levels.
• Execute gate-level simulations, including timing-annotated and power-aware (UPF) verification.
• Utilize tools such as assertions, formal verification, HW-SW co-verification, and emulation.

Requirements

• Bachelor's degree in Computer Science, Electrical/Electronics Engineering, or a related field.
• 2+ years of experience in processor or ASIC design verification.
• Expertise in SystemVerilog and UVM testbench architecture and implementation.
• Solid understanding of Digital Design, Processor Architecture, and Power-aware verification.
• Proficiency in scripting and automation using Python, Perl, Shell, or Make.
• Strong analytical and debugging skills with knowledge of Object-Oriented Programming (OOP) concepts.

Preferred Qualifications

• Experience writing C-based and assembly-level testcases.
• Exposure to power-aware implementation and verification using UPF.
• Experience with advanced verification techniques such as formal verification and assertions.
• Experience with verification of Processor subsystems.
• Proficiency with simulators from Synopsys, Mentor, or Cadence.

About the Company

Qualcomm is a leading technology innovator that pushes the boundaries of what's possible to enable next-generation experiences and drive digital transformation for a smarter, connected future. As one of the largest fabless semiconductor design companies in the world, we develop cutting-edge solutions for mobile, AI, automotive, and IoT markets.