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Posted 2 hours ago
Distinguished Engineer, Formal Verification
Astera LabsDistinguished Engineer, Formal Verification
Requirements
15+ years formal verification experience, SystemVerilog/Verilog proficiency, Python or Perl scripting, Bachelor's degree in EE, CE, or CS
Skills
SystemVerilogPython
About the role
Responsibilities
- Define and evolve formal verification strategy, methodologies, and best practices across all product lines
- Serve as the technical authority on formal verification and provide expert guidance to engineering leadership
- Represent Astera Labs in industry forums, standards bodies, and technical conferences
- Develop detailed formal verification test plans and collaborate with design teams to refine micro-architecture specifications
- Implement formal verification models, abstractions, assertions, and utilize assertion-based model checking
- Apply complexity reduction techniques using industry-standard EDA tools
- Mentor Principal and Lead Engineers across global sites in advanced formal verification techniques
- Participate in design reviews to optimize design quality and PPA metrics
Requirements
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field
- 15+ years of experience in formal verification or 18+ years in traditional design verification with formal specialization
- Strong proficiency in SystemVerilog/Verilog
- Advanced scripting abilities with Python or Perl
- Proven ability to manage high-impact tasks in a fast-paced environment
- Strong cross-functional collaboration and influence skills
Preferred Qualifications
- Master's or PhD in Electrical Engineering, Computer Engineering, Computer Science, or Mathematics
- Hands-on experience with Synopsys VCFormal or Cadence JasperGold
- Experience with both bug hunting and static proof verification techniques
- Familiarity with automating formal verification workflows within CI/CD
- Deep knowledge of high-speed serial protocols (PCIe, CXL, Ethernet, UCIe, UALink)
- Participation in industry standards bodies (PCI-SIG, CXL Consortium, IEEE, UCIe)
- Patents or publications in formal verification methodologies
About the Company
Astera Labs provides rack-scale AI infrastructure through purpose-built connectivity solutions, enabling organizations to unlock the full potential of modern AI through its Intelligent Connectivity Platform.
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Get started — it's freeDistinguished Engineer, Formal Verification
Astera Labs · San Jose
