Director, Physical Design

About the Company

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. Our semiconductor products power the world's leading cloud service providers, hyperscalers, and server OEMs.

Responsibilities

• Build, lead, and mentor a high-performing Physical Design team in Hyderabad across PnR, STA, EMIR/Power Integrity, and CAD/methodology functions
• Own end-to-end physical implementation of complex SoCs/ASICs from floor planning through GDSII signoff
• Drive floor planning, placement, clock tree synthesis (CTS), routing, timing closure, power analysis, and physical verification
• Establish and continuously improve PD flows, methodologies, and best practices
• Evaluate and deploy EDA tools and drive automation via scripting
• Partner with RTL, DV, DFT, packaging, and architecture teams to ensure seamless integration of complex subsystems

Requirements

• Bachelor's or master’s degree in electrical engineering, Electronics, or Computer Science
• 18+ years of experience in ASIC physical design
• 5+ years in a leadership or management role
• Proven track record of multiple successful tapeouts at advanced nodes (7nm or below)
• Deep expertise in floorplanning, PnR, CTS, STA, IR/EM analysis, and physical verification
• Proficiency with Cadence Innovus, Synopsys Fusion Compiler, PrimeTime, Calibre, and RedHawk/Voltus
• Experience with high-speed interface IPs (SerDes, PCIe, CXL, or D2D)
• Strong scripting skills in Tcl, Python, or Perl

Preferred Qualifications

• Experience with chiplet architecture, UCIe interfaces, or die-to-die physical integration
• Familiarity with low-power design techniques (UPF/CPF)
• Experience working with TSMC advanced nodes and tapeout processes
• Background in networking, storage, or AI/ML SoC designs
• Experience establishing a PD center of excellence or greenfield PD team