Digital Verification Manager

Responsibilities

• Define and own end-to-end verification strategy, including planning, coverage closure, and sign-off
• Architect and develop reusable UVM-based environments for digital and mixed signal IPs
• Oversee AMS co-simulation strategies using real-number modeling and behavioral analog models
• Collaborate with RTL design, architecture, and mixed signal teams for seamless IP integration
• Own verification schedules, resource planning, and risk mitigation
• Lead, mentor, and grow the verification team, including hiring and performance reviews

Requirements

• Bachelor's or Master's degree in Electrical or Computer Engineering
• 12+ years of experience in VLSI Digital Design/Verification
• 3-5+ years in a people management or technical lead role
• Strong command of UVM and System Verilog
• Experience with constrained-random, coverage-driven, and assertion-based verification
• Proficiency in Python, Perl, TCL, or Shell scripting
• Experience with mixed signal verification and AMS co-sim
• Proven track record of taking IPs from spec to silicon-proven delivery

Preferred Qualifications

• Knowledge of clock and reset domain crossing techniques
• Familiarity with ISO 26262 or functional safety standards
• Experience with SERDES PHYs and Protocols
• Experience using version control and bug tracking software

About the Company

Mixel, a Silvaco Company, is an innovator of high-performance analog mixed signal semiconductor IPs powering Mobile, Display, Camera, Automotive, VR, AR and AI applications.