Digital Verification Engineer Prime (FEC)

Responsibilities

• Read and understand FEC architecture and functional requirements to collaborate with designers, modelers, and architects
• Develop verification, functional coverage, and formal verification test plans
• Validate architectural FEC functional blocks using simulation, formal, and coverage methods
• Create testbench environments, components, agents, scoreboards, and test scenarios using System Verilog UVM and C++
• Perform coverage-driven verification, monitor regressions, and debug failures
• Mentor and supervise junior verification engineers to foster technical and professional growth
• Provide regular status updates on verification progress and communicate potential risks

Requirements

• 10+ years of experience in digital verification
• Bachelor's degree in Electrical, Computer, or Software Engineering
• Significant experience with C/C++, System Verilog, UVM, SVA, and major vendor simulators
• Proven ability to determine comprehensive digital verification and coverage strategies
• Strong decision-making and problem-solving skills regarding complex technical situations

Preferred Qualifications

• Experience with formal verification methods
• Strong background in Forward Error Correction (FEC) and/or DSP
• Familiarity with Python, Make, bash, and object-oriented programming
• Proficiency in Jira for bug tracking and GIT for source code management
• Previous experience in team leadership and mentoring

About the Company

Ciena is a global leader in high-speed connectivity, committed to a people-first approach. We drive business priorities alongside meaningful social, community, and societal impact, fostering a culture that prioritizes flexibility, individual growth, and belonging.