Digital Verification Engineer Expert

Responsibilities

• Propose and implement innovative verification strategies to validate functional blocks, cores, and subsystems for the Wavelogic product family
• Perform complete and detailed validation of entire subsystems using simulation, formal, and coverage methods
• Create, review, and optimize simulation environment components, test case scenarios, functional coverage, and formal verification test plans
• Collaborate with systems engineers and architects to understand project architecture and functional requirements
• Lead focused groups or mentor individuals to achieve specific technical objectives
• Estimate schedules and provide precise status updates to management

Requirements

• Bachelor’s degree in Electrical or Computer Engineering, Computer Science, or a related scientific field
• Expert-level experience with SystemVerilog, UVM, and SVA
• Proven ability to develop comprehensive digital verification and coverage strategies
• Experience using simulators from major vendors
• Ability to methodically debug sophisticated technical problems
• Strong organization and written/oral English communication skills

Preferred Qualifications

• Experience with formal verification methods
• Knowledge of DSP and/or Forward Error Correction
• Proficiency with Jira for bug tracking and GIT for source code management
• Familiarity with programming languages such as Python, Make, bash, C, or C++

Benefits

• Competitive annual salary range
• Comprehensive medical, dental, and vision plans
• 401(k) participation with company matching
• Employee Stock Purchase Program (ESPP)
• Employee Assistance Program (EAP)
• Paid holidays, sick leave, and vacation time

About the Company

Ciena is a global leader in high-speed connectivity, providing optical fiber transmission solutions that drive the telecommunications industry. We are a technology company that leads with humanity, prioritizing a flexible work environment that empowers individual growth, well-being, and belonging.