Digital Verification Engineer

Responsibilities

• Implement innovative verification strategies to simulate and validate functional blocks and subsystems for the Wavelogic family of products
• Read and understand functional requirements specification documents and collaborate with systems engineers and architects
• Perform complete validation of functional blocks using simulation, formal, and coverage methods
• Create verification, functional coverage, and formal verification test plans
• Develop testbench environments, components, agents, and scoreboards using SystemVerilog UVM and/or C
• Execute coverage-driven verification, monitor regressions, and debug failures in collaboration with designers
• Provide regular status updates on verification progress

Requirements

• BEng/BSc or MEng/MSc in Electrical/Computer Engineering, Computer Science, or a related scientific field
• Proficiency above the intermediate level with SystemVerilog, SVA, and major vendor simulators
• Proven ability to determine appropriate and comprehensive digital verification and coverage strategies
• Strong ability to methodically solve complex technical problems
• Excellent organization and written/oral English communication skills
• Ability to work independently as a self-starter while remaining a productive team player

Benefits

• Medical, dental, and vision plans
• 401(K) participation with company matching
• Employee Stock Purchase Program (ESPP)
• Employee Assistance Program (EAP)
• Company-paid holidays, paid sick leave, and vacation time
• Discretionary incentive bonus eligibility

About the Company

Ciena is a global leader in high-speed connectivity, committed to a people-first approach. We drive business priorities alongside meaningful social, community, and societal impact, fostering a culture that prioritizes flexibility, individual growth, and belonging.