Digital Verification Development Engineer

Responsibilities

• Develop test plans from specification and architect system level verification environments
• Develop and maintain UVM-based testbenches for block-level and subsystem-level verification
• Write constrained-random stimulus, scoreboards, monitors, and coverage models in SystemVerilog
• Contribute to regression infrastructure, continuous integration flows, and internal verification methodology
• Drive functional and code coverage closure; analyze coverage holes and add targeted tests
• Integrate and configure VIP (Verification IP) for standard protocols
• Support FPGA-based prototyping and pre-silicon bring-up with validation test suites
• Execute RTL/Gate level simulations and analyze results
• Contribute to design/verification process automation

Requirements

• Bachelor’s degree in Electronics or Computer Engineering
• 0-3 years of experience in developing SV-based verification environments
• Strong knowledge of Verilog, SystemVerilog, and object-oriented programming languages
• Strong proficiency in UVM methodology
• Solid understanding of functional and code coverage metrics and closure
• Fluency in English
• Proficiency in Unix/Linux operating systems

Preferred Qualifications

• Familiarity with RTL design, synthesis, and CDC analysis
• Working knowledge of shell, Perl, and TCL scripting

About the Company

Mixel, a Silvaco Company, is an innovator of high-performance analog mixed signal semiconductor IPs whose solutions are powering Mobile, Display, Camera, Automotive, VR, AR and AI applications.