Digital Senior Design Engineer

Responsibilities

• Propose innovative solutions to design power and area optimized functional blocks for the Wavelogic family of products
• Read and understand architecture and functional requirements to collaborate with systems engineers and architects
• Produce implementation specification documents and manage the creation and integration of RTL and/or C source code
• Perform designer testing and debugging of code during simulation and regression verification
• Assist verification teams with coverage determination, design assertions, and waivers
• Craft timing constraints and participate in synthesis log reviews, timing report analysis, and backend reviews
• Support lab validation of products and prototypes

Requirements

• BEng/BSc or MEng/MSc in Electrical or Computer Engineering
• Proficiency in SystemVerilog for design
• Experience with digital design synthesis, STA, timing closure, and asynchronous clock crossing
• Strong understanding of timing, power, and area analysis and trade-offs
• Familiarity with digital and formal verification methods
• Excellent organization and English communication skills

Preferred Qualifications

• Experience with digital silicon design backend processes and low-power design
• Knowledge of standards and protocols such as OTN, FlexO, B100G, or Ethernet (100GE+)
• Proficiency with GIT for source code management and Jira for task tracking
• Experience with programming languages including Python, C, C++, SystemC, or Bash

About the Company

Ciena is a global leader in high-speed connectivity, providing optical fiber transmission solutions. We are a technology company that leads with humanity, prioritizing a flexible work environment that empowers individual growth, well-being, and belonging.