Digital IP Principal Verification Engineer

Responsibilities

• Define and implement design verification strategies for IP or sub-system levels.
• Execute digital functional verification to ensure compliance with product architecture specifications.
• Author verification content, including documentation, functional simulation models, and testbench environments.
• Write stimulus using SystemVerilog (UVM), including random test scenarios and directed testcases.
• Develop and maintain verification environments, scripts, and makefiles.
• Debug failing testcases to identify sources of failure in tools, testcases, checkers, or RTL.
• Analyze code and functional coverage results to achieve 100% coverage.
• Perform assertion-based formal verification of blocks and IPs.
• Utilize AI tools to augment the generation of work products and increase productivity.

Requirements

• Minimum BSEE, BSCE, or BSCS degree (MSEE/MSCE/MSCS preferred).
• At least 6 years of experience in IP or SoC design or verification.
• Strong coding skills in Verilog, SystemVerilog, and UVM.
• Proven verification skills including test planning, testcase development, testbench creation, simulation, and debugging.
• Proficiency in using AI to enhance productivity and work product generation.
• Ability to work independently and effectively within small teams.

Preferred Qualifications

• Programming skills in Python, C/C++, Perl, or TCL.
• Design experience including RTL coding, synthesis, and static/formal checkers.
• Knowledge of ARM AMBA® protocols.

About the Company

NXP Semiconductors enables a smarter, safer, and more sustainable world through innovation. As a global leader in secure connectivity solutions for embedded applications, NXP pushes boundaries in the automotive, industrial & IoT, mobile, and communication infrastructure markets.