Digital Design Verification, Principal Engineer/Architect

Responsibilities

• Architect and implement unified verification flows for digital IP products using VCS, Verdi, VMS Execution Manager, and VIPs
• Build scalable verification infrastructure from the ground up to support complex IP and SoC projects across global teams
• Define, document, and propagate verification methodologies and best practices as company standards
• Lead and mentor verification engineers, providing technical guidance on UVM, SystemVerilog, and debugging strategies
• Collaborate with EDA tool development teams to influence product roadmaps and optimize verification workflows
• Troubleshoot and refine verification processes to diagnose and resolve flow bottlenecks

Requirements

• 10+ years of hands-on experience in IP or SoC verification
• Deep expertise with Synopsys verification tools including VCS, Verdi, VMS Execution Manager, Verdi Planner (HVP), and Verification IP (VIP)
• Strong programming and scripting skills in SystemVerilog, UVM, Tcl, and Python
• Demonstrated ability to architect verification flows and infrastructure for complex digital designs
• Bachelor's degree in Electronics, Electrical, or Computer Engineering

About the Company

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services to power innovation across a wide range of industries.