Digital Design Verification Engineer

About the Company

OLIX is building the next generation of AI infrastructure. The OLIX Decode Accelerator 1 (DX-1) is the first accelerator architected specifically for decode, utilizing rack-scale co-design of logic, data movement, packaging, optics, and interconnect to achieve a step change in system-level performance.

Responsibilities

• Own end-to-end verification of high-throughput digital pipelines supporting multi-GSPS input rates and continuous streaming data paths
• Develop and maintain comprehensive verification environments using SystemVerilog/UVM, including constrained-random testing and coverage closure
• Define and implement assertion-based verification strategies for control logic, data-path correctness, and protocol compliance
• Apply formal verification techniques to complement simulation-based verification
• Model and validate algorithms using MATLAB/Simulink or Python to ensure functional equivalence from models through RTL
• Support FPGA prototyping and silicon bring-up by developing targeted testcases and debug strategies
• Collaborate with digital design, optical-hardware, mixed-signal, and software teams

Requirements

• 5+ years of hands-on experience in digital verification for high-performance ASICs or SoCs
• Ownership of verification for complex blocks or subsystems processing real-time data streams
• Strong proficiency in SystemVerilog, assertions (SVA), and modern verification methodologies (UVM, CocoTB)
• Proven experience verifying designs in GHz-class clock domains, including CDC/RDC analysis
• Familiarity with industry-standard EDA flows (RTL simulation, formal verification, linting, STA, UPF/CPF)
• Experience verifying high-speed IP such as SerDes, DDR/HBM, PCIe, or Ethernet
• Proficiency with MATLAB/Simulink or Python/NumPy for algorithm modelling and test-vector generation
• Solid grounding in digital design, computer architecture, and DSP fundamentals

Preferred Qualifications

• Tape-out experience at 22 nm or below
• Deep experience with formal verification tools such as Jasper
• Exposure to coherent optical links or photonic-electronic co-design
• Familiarity with AI/ML workloads, systolic arrays, or tensor-processing architectures
• Expertise in arithmetic pipeline, processor, or ISA verification

Benefits

• Competitive Salary
• Meaningful stock options
• Annual Living-Local Bonus for residents within 20 minutes of the office
• Employer-contributed retirement plans