Digital Design Manager

Responsibilities

• Responsible for micro-architecture specification and RTL design of modules in Verilog
• Lead development teams in the development of digital controllers through the full project lifecycle
• Lead verification teams to develop advanced test plans
• Perform hardware verification of digital modules using FPGA kits
• Provide technical leadership, project direction, and mentoring to the team
• Own delivery schedules, resource planning, and risk mitigation across concurrent projects
• Engage with customers and partners on IP deliverables and integration support
• Foster a culture of technical excellence and continuous improvement

Requirements

• Bachelor’s degree in Electronics or Computer Engineering
• 12+ years of experience in VLSI Digital Design/Verification
• 3-5+ years in a people management or technical lead role
• Proven track record of taking IPs from spec to silicon-proven delivery
• Strong knowledge of Verilog RTL design and simulation
• Proficiency in ASIC/FPGA design flows (RTL Synthesis, Place and Route, Timing Sign-off)
• Strong knowledge of CDC and RDC techniques
• Experience with System Verilog, UVM, and RTL/gate verification
• Proficiency in Python, Perl, TCL, or Shell scripting
• Experience working with global teams

Preferred Qualifications

• Master’s Degree
• Knowledge of high level synthesis techniques and C-simulation/validation

About the Company

Mixel is a leading provider of high-performance mixed-signal IPs integrated into applications such as smartphones, automotive, IoT, wearables, and sensors.