Digital Design Engineer Prime (FEC)

Responsibilities

• Implement industry standard and custom subsystems for Ciena’s Forward Error Correction (FEC) IP within the Wavelogic modem product family
• Read and understand architecture and functional requirements to collaborate with systems engineers, DSP systems, and architects
• Produce implementation specification documents and manage the creation and integration of new and existing RTL and/or C source code
• Work independently to develop detailed design specifications for IP subcomponents through all stages of design
• Perform designer testing and debugging of code during simulation and regression verification
• Assist the verification team with coverage determination, design assertions, and waivers
• Create timing constraints and participate in synthesis log reviews, constraint reviews, and timing report analysis
• Mentor and supervise junior engineers to foster technical and professional growth

Requirements

• 10+ years of ASIC/FPGA design experience successfully delivering complex designs
• Bachelor's degree in Electrical or Computer Engineering
• Proficiency in C/C++, System Verilog, synthesis, and power analysis
• Experience with SDC, STA, and CDC
• Experience with high level synthesis (HLS) tools and methodologies
• Proven ability to implement designs to timing closure

Preferred Qualifications

• Strong background in Forward Error Correction (FEC) and/or DSP
• Familiarity with Python, Make, bash, and object-oriented programming
• Experience with design for low power
• Proficiency in Jira for bug tracking and GIT for source code management
• Previous experience leading or mentoring a team

About the Company

Ciena is a global leader in high-speed connectivity, committed to a people-first approach. We drive business priorities alongside meaningful social, community, and societal impact, providing a flexible work environment that empowers individual growth and well-being.