Digital Design Engineer

Responsibilities

• Develop a thorough understanding of system-level design specifications
• Verilog RTL Coding, Synthesis, and Simulation of digital IPs
• Develop advanced verification environments and test-bench components
• Conduct RTL linting, CDC/RDC checks, and formal verification
• Perform synthesis, timing analysis, and collaborate with physical design teams on DFT and timing closure
• Hardware verification of digital modules using FPGA kits
• Gate level verification of digital IPs

Requirements

• Bachelor’s degree in Electronics Engineering (M.Sc. is a plus)
• 0-3 years of experience in VLSI Digital Design/Verification
• Strong knowledge of Verilog RTL design and simulation
• Knowledge of clock domain crossing (CDC) and reset domain crossing (RDC) techniques
• Knowledge of ASIC/FPGA design flows including RTL Synthesis, Place and Route, and Timing Sign-off
• Solid understanding of static timing analysis (STA) and timing constraints (SDC)

Preferred Qualifications

• Familiarity with System Verilog and UVM
• Knowledge of RTL/gate verification techniques
• Knowledge of Unix/Linux operating systems
• Knowledge of shell scripting or programming languages

About the Company

Mixel, a Silvaco Company, is an innovator of high-performance analog mixed signal semiconductor IPs whose solutions are powering Mobile, Display, Camera, Automotive, VR, AR and AI applications.