DFT Engineer

About the Company

Etched is building hardware for frontier intelligence. We co-design chips, racks, software, and manufacturing to deliver best-in-class throughput and latency across both prefill and decode workloads. We are a fully in-person team in San Jose (Santana Row).

Responsibilities

• Develop and implement robust DFT architectures for ASIC and SoC designs
• Integrate industry-standard DFT methodologies such as scan insertion, boundary scan, BIST, and MBIST
• Collaborate cross-functionally with design and verification teams
• Analyze test results and silicon debug data to drive improvements in coverage, yield, and reliability
• Create and execute comprehensive DFT verification plans
• Support silicon bring-up, debug, and failure analysis during post-silicon validation
• Partner with test engineering teams to optimize ATE programs for volume production
• Author and maintain detailed documentation for DFT architecture and test plans

Requirements

• 10+ years of experience in DFT engineering with successful ASIC or SoC implementations
• Deep understanding of digital design and verification methodologies
• Proficiency in System Verilog
• Fluency with industry-standard EDA tools (Synopsys DFT Compiler, Cadence Encounter Test, Mentor Tessent)
• Scripting experience using Python, Perl, or TCL
• Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field

Preferred Qualifications

• Master's degree in a related field
• Experience with mixed-signal DFT methodologies
• Knowledge of IEEE 1149.1 (JTAG) and IEEE 1500 standards
• Experience in yield analysis and product engineering

Benefits

• Medical, dental, and vision packages
• $500 per month credit for waiving medical benefits
• $2k per month housing subsidy for those living within walking distance of the office
• Relocation support for San Jose
• Wellness benefits covering fitness and mental health
• Daily lunch and dinner in the office
• Unlimited compute budget subject to ROI justification