DFT Design Engineering Director

Responsibilities

• Define and drive the comprehensive DFT strategy for PCIe Gen3/4/5/6 switch products with 2.5D/3D packaging
• Lead and mentor a team of DFT engineers across multiple product development cycles
• Develop DFT strategies for 2.5D/3D heterogeneous integration architectures including multi-die test access, TSV testing, and Known Good Die (KGD) strategies
• Architect test access mechanisms for inter-die communication, HBM/DRAM interfaces, and power delivery networks
• Implement advanced DFT features such as scan insertion, ATPG, MBIST, LBIST, and IEEE 1838 (3D-DFT) standards
• Drive fault coverage targets and optimize test time and ATE costs
• Partner with physical design, packaging, and silicon validation teams to optimize DFT area, timing, and post-silicon debug
• Collaborate with manufacturing and OSAT partners for seamless production ramp and yield enhancement

Requirements

• MS or PhD in Electrical Engineering, Computer Engineering, or related field
• 12+ years of experience in DFT engineering with complex SoC/ASIC products
• 5+ years of hands-on experience with 2.5D and/or 3D packaging DFT strategies
• 5+ years in technical leadership or management roles
• Proven track record of multiple successful tape-outs with high-volume production
• Deep expertise in DFT methodologies and industry standards (IEEE 1149.1, 1687, 1838)
• Experience with DFT EDA tools such as Synopsys or Mentor Tessent
• Strong background in silicon interposer-based designs, TSV technology, and chiplet architectures
• Familiarity with ATE platforms like Advantest or Teradyne

Preferred Qualifications

• Experience with PCIe, CXL, or other high-speed serial protocols
• Background in SerDes architecture and testing
• Experience with HBM (High Bandwidth Memory) testing in 2.5D packages
• Knowledge of chiplet-based system architectures (UCIe, BoW, AIB)
• Familiarity with 3D stacking technologies and wafer-level testing
• Experience with functional safety requirements (ISO 26262)

About the Company

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI.