DFT Consultant

Responsibilities

• End-to-end DFT implementation at block and top level including SCAN, MBIST, LBIST, BSCAN, and IJTAG
• Define and implement IEEE 1149.1 JTAG & IJTAG architectures
• Perform hierarchical scan insertion and full-chip DFT integration
• Execute complete ATPG flow including coverage analysis and debug
• Drive coverage improvement and LBIST coverage analysis
• Support gate-level simulation (GLS) enablement
• Perform RTL-level DFT verification, lint checks, and equivalence checks
• Develop ATE patterns and support silicon bring-up and post-silicon debug
• Collaborate with RTL, Physical Design, Verification, and Test teams
• Support test strategy and integration for Analog IPs

Requirements

• 6+ years of hands-on experience in DFT
• Strong expertise in SCAN, MBIST, LBIST, BSCAN, IJTAG, and IP test modes
• Proficient in ATPG coverage analysis, DFT debug, and verification
• Experience with Siemens Tessent, Cadence Genus, Synopsys Fusion Compiler, VCS, Conformal/Formality, and SpyGlass
• Scripting skills in Perl, TCL, and/or Python
• B.E./B.Tech/M.E./M.Tech in ECE, EE, VLSI, or Computer Engineering

Preferred Qualifications

• Experience with advanced nodes and low-power DFT techniques
• Exposure to automotive or safety-critical designs
• Full silicon lifecycle experience from RTL to production