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Posted 8 hours ago
Design Verification Intern
EtchedDV Intern
Perks & benefits
Paid LeaveHousing AllowanceRelocation Allowance
Requirements
Degree progress in EE or CE, High-speed digital logic familiarity, ASIC or SoC design exposure, SystemVerilog, UVM, or Python familiarity, Verification and test bench experience, Physical design flow familiarity
Skills
SystemVerilogUVMPython
About the role
About the Company
Etched is building hardware for frontier intelligence. We co-design chips, racks, software, and manufacturing to deliver best-in-class throughput and latency across both prefill and decode workloads. Our first products are heavily focused on inference.
Responsibilities
- Ensure custom IPs powering chips, including systolic arrays, DMA engines, and NoCs, are robust and silicon-ready
- Collaborate with architects, RTL designers, and SW/FW/emulation teams to validate correctness and performance
- Tackle complex verification challenges across the full hardware-software stack
Requirements
- Progress towards a Bachelor’s, Master’s, or PhD in electrical engineering, computer engineering, or a related field
- Familiarity with high-speed digital logic
- Exposure to ASIC or SoC design concepts
- Familiarity with SystemVerilog, UVM, or Python
- Familiarity with verification work and writing test benches
- Familiarity with physical design flows and tooling
- Ability to learn quickly about transformers and modern AI
Preferred Qualifications
- Familiarity with modern ML and LLM model architectures
- UVM or formal verification experience
- Ability to program with Python or another scripting language
Benefits
- 12-week paid internship
- Generous housing support for those relocating
- Daily lunch and dinner in our office
- Direct mentorship from industry leaders and world-class engineers
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Etched · San Jose
