Design Verification Engineer - SoC

About the Company

Etched is building hardware for frontier intelligence. We co-design chips, racks, software, and manufacturing to deliver best-in-class throughput and latency across both prefill and decode workloads. Our first products are heavily focused on inference.

Responsibilities

• Work with architects and RTL designers to verify performance features and correlate with performance models
• Collaborate with software and application developers to identify and tune performance bottlenecks
• Develop test plans, infrastructure, and tools for performance tuning and verification
• Improve and maintain architectural performance models
• Develop tests in SystemVerilog, Python, or vectors to debug and correlate RTL and performance models
• Develop SystemVerilog or Python-based checkers and coverage monitors
• Debug performance issues and conduct performance tuning on silicon
• Drive end-to-end performance tuning across the ASIC design lifecycle

Requirements

• Strong understanding of digital design, RTL, and ASIC design flows
• Hands-on experience with performance verification, simulation, and modeling
• Proficiency in developing checkers, coverage monitors, and testbenches in SystemVerilog
• Skilled in writing Python scripts for automation, data analysis, and performance modeling
• Experience building and maintaining performance models for chip subsystems
• Understanding of memory hierarchies, pipelines, interconnects, and compute accelerators
• Familiarity with performance bottleneck analysis, compiler optimizations, and workload tuning
• Exposure to kernel level performance metrics and profiling tools

Benefits

• Medical, dental, and vision packages with generous premium coverage
• $500 per month credit for waiving medical benefits
• Various wellness benefits covering fitness and mental health
• Daily lunch and dinner in the office
• Unlimited compute budget subject to ROI justification