Design Verification Engineer

Responsibilities

• Collaborate with Digital, Analog, and Verification teams on system requirements
• Participate in the development of Verification Plans and Environments
• Develop and verify self-checking testbenches using Verilog and SystemVerilog
• Write and execute directed and constrained-random tests to improve coverage
• Debug and report design issues and drive root-cause analysis with design teams
• Learn and apply verification methodologies including UVM under senior guidance
• Support regression runs and analyze simulation results
• Document test plans, results, and findings clearly and accurately

Requirements

• BS in Electrical Engineering, Computer Engineering, or a related field with up to 2 years of experience, or an MS with no experience
• Coursework or project experience in digital design and verification
• Familiarity with Verilog or SystemVerilog
• Basic understanding of analog and digital circuit concepts
• Strong analytical, problem-solving, and debugging skills
• Good written and verbal communication skills

Preferred Qualifications

• Exposure to UVM (Universal Verification Methodology)
• Understanding of power electronics concepts such as DC-DC converters, LDOs, or PMICs
• Experience with simulation tools like Cadence Virtuoso
• Familiarity with scripting languages such as Python or Perl
• Knowledge of Real Number Modeling (RNM) or VerilogAms Modeling
• Internship or research experience in VLSI design or verification

About the Company

Renesas is an embedded semiconductor solution provider driven by its purpose to make our lives easier. As a leading expert in embedded processing, we provide scalable semiconductor solutions for the automotive, industrial, infrastructure, and IoT industries. With a diverse team of over 22,000 professionals globally, we design and develop sustainable, power-efficient solutions that help communities thrive.