Posted 9 hours ago
Design Verification Engineer
OpenAIDesign Verification Engineer
Requirements
BS/MS in EE/CE/CS, 3+ years hardware verification experience, Proficiency in SystemVerilog and UVM, Knowledge of computer architecture
Skills
SystemVerilogUVMSOC
About the role
Responsibilities
- Own the verification of custom IP blocks, subsystems, or full-chip SoC-level functionality
- Define verification plans based on architecture and microarchitecture specs
- Develop constrained-random, directed, and system-level testbenches using SystemVerilog/UVM
- Build and maintain stimulus generators, checkers, monitors, and scoreboards
- Drive bug triage, root cause analysis, and work with design teams on resolution
- Contribute to regression infrastructure, coverage analysis, and closure
Requirements
- BS/MS in EE/CE/CS or equivalent
- 3+ years of experience in hardware verification
- Proven success verifying complex IP or SoC designs
- Proficiency in SystemVerilog, UVM, and simulation/debug tools (VCS, Questa, Verdi)
- Strong knowledge of computer architecture, memory/cache systems, coherency, and interconnects
Preferred Qualifications
- Familiarity with performance modeling, formal verification, or emulation
- Experience in fast-paced, cross-disciplinary teams
About the Company
OpenAI is an AI research and deployment company dedicated to ensuring that general-purpose artificial intelligence benefits all of humanity.
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OpenAI · San Francisco
