Design Verification Engineer

Responsibilities

• Provide design verification for internal hardware projects
• Create testbench environments, assertions, and coverage from design documents
• Set up and evaluate EDA tools for internal usability and deployment
• Review AI-generated collateral to shape product strategy and refine outputs
• Curate and annotate datasets to associate chip specifications with test cases
• Implement automated QA and data augmentation for ML training
• Generate synthetic data using AI-based methods
• Build automated pipelines to annotate test data and link it to chip specifications
• Automate document parsing for contextual tagging and traceability

Requirements

• 5+ years of experience in Digital Verification at a semiconductor or EDA company
• Advanced proficiency in SystemVerilog and UVM methodology
• Experience with EDA verification tools such as vManager, Xcelium, or Jasper
• Proficiency in Python or Perl scripting
• Expertise in end-to-end design verification, test plan creation, and stimulus generation
• Excellent written and spoken communication skills

About the Company

Normal Computing builds silicon that turns thermal noise from an obstacle into a computational resource. We co-design the full stack, from AI-native EDA systems to advanced ASICs, aiming for 10-100x more AI inference per dollar and per watt.