Design Verification Engineer - Machine Learning Accelerators

Responsibilities

• Work with cross-functional leads to develop industry-leading Machine Learning IP optimized for Mixed Reality and Smart Devices
• Define, track, and lead the execution of detailed test plans for various modules and top levels
• Implement scalable test benches including checkers, reference models, and assertions in SystemVerilog
• Drive Design Verification to closure based on defined functional and code coverage metrics
• Collaborate with Design, Model, Emulation, and Silicon validation teams to ensure design quality across the product lifecycle
• Support the integration of developed subsystems and IP blocks into larger SoC environments
• Develop and drive continuous improvements in verification using the latest industry methodologies and tools

Requirements

• 10+ years of hands-on experience in SystemVerilog/UVM methodology and C/C++ based verification
• 10+ years of experience in IP/sub-system and/or SoC level verification
• Experience with SV Assertions, Formal, or Emulation
• Proficiency with EDA tools and scripting languages such as Python, TCL, Perl, or Shell
• Bachelor's degree in Computer Science, Computer Engineering, or a relevant technical field

Preferred Qualifications

• Master's degree in Electrical Engineering or Computer Science
• 5+ years of experience with Design verification/validation of machine learning applications and accelerators
• 5+ years of experience with Software/Hardware Co-design at firmware, ISA, and application levels
• 5+ years of experience with low power design or numerical compute-based designs
• Experience with revision control systems like Git or Mercurial
• FPGA or emulation debug experience

About the Company

Meta builds technologies that help people connect, find communities, and grow businesses. Reality Labs focuses on delivering Meta's vision through Augmented Reality (AR) and Smart Devices, driving breakthrough work in computer vision, machine learning, and mixed reality.