Design Verification Engineer

About the Company

Etched is building hardware for frontier intelligence. We co-design chips, racks, software, and manufacturing to deliver best-in-class throughput and latency across both prefill and decode workloads. Our first products are heavily focused on inference.

Responsibilities

• End to end ownership of IP subsystems including PCIe, Ethernet, CPU (arc/arm), low power peripherals, or sensors
• Understand vendor IP configurations and handle handshake with internal IP teams
• Develop and maintain UVM/SystemVerilog-based verification environments
• Collaborate with integration and SoC DV teams to validate external IP interaction
• Drive coverage closure and sign-off by defining metrics and analyzing gaps

Requirements

• 5+ years of design verification experience
• Hands-on experience with SystemVerilog and UVM
• Experience with standard IP interfaces such as PCIe, Ethernet, AXI/AMBA, or ARM/ARC CPUs
• Ability to work in a fast-paced startup environment

Preferred Qualifications

• Experience handling vendors and integration of IP/VIPs
• Expertise in UVM and SystemVerilog