Design Verification Engineer

About the Company

Etched is building hardware for frontier intelligence. We co-design chips, racks, software, and manufacturing to deliver best-in-class throughput and latency across both prefill and decode workloads. Our first products are heavily focused on inference.

Responsibilities

• Develop and maintain UVM/SystemVerilog testbenches for high-performance IPs (compute arrays, DMAs, NoCs, memory subsystems)
• Define and execute verification plans covering functional correctness, corner cases, concurrency, and performance bottlenecks
• Debug complex datapath and protocol issues in RTL and testbench environments
• Work closely with architects and designers to validate functionality and design intent
• Partner with SW, FW, and emulation teams to ensure end-to-end bring-up and debug coverage
• Contribute to reusable DV infrastructure, coverage models, and methodology improvements

Requirements

• Proficiency with UVM and SystemVerilog
• Strong debugging and problem-solving skills for complex digital designs
• Solid knowledge of computer architecture and digital design fundamentals
• Hands-on experience verifying datapaths, memory systems, interconnects, or high-throughput fabrics

Preferred Qualifications

• Familiarity with SystemVerilog Assertions (SVA) and formal verification techniques
• Experience verifying systolic arrays, DMA engines, or NoC/AXI protocols
• Scripting skills (Python/Perl/TCL or similar) for automation, debug and regression flows

Benefits

• Medical, dental, and vision packages with generous premium coverage
• $500 per month credit for waiving medical benefits
• Housing subsidy of $2k per month for those living within walking distance of the office
• Relocation support for those moving to San Jose
• Various wellness benefits covering fitness, mental health, and more
• Daily lunch + dinner in our office
• Unlimited compute budget subject to ROI justification