Design Verification Engineer

About the Company

Etched is building hardware for frontier intelligence. We co-design chips, racks, software, and manufacturing to deliver best-in-class throughput and latency across both prefill and decode workloads. Our first products are heavily focused on inference.

Responsibilities

• End to end ownership of IP subsystems including PCIe, Ethernet, CPU (arc/arm), low power peripherals, and sensors
• Understand vendor IP configurations and handle handshake with internal IP team
• Develop and maintain UVM/SystemVerilog-based verification environments to ensure functional correctness, performance, and compliance
• Collaborate with integration and SoC DV teams to validate seamless interaction of external IPs within the broader chip architecture
• Drive coverage closure and sign-off by defining metrics, analyzing gaps, and ensuring comprehensive verification across corner cases and stress scenarios

Requirements

• 5+ years of design verification experience
• Hands-on experience with SystemVerilog/UVM
• Experience with standard IP interfaces and protocols such as PCIe, Ethernet, AXI/AMBA, or ARM/ARC CPUs
• Ability to work in a fast-paced startup environment
• Strong cross-functional collaboration skills

Preferred Qualifications

• Experience handling vendors and integration of IP/VIPs
• Advanced UVM/System Verilog expertise

Benefits

• Medical, dental, and vision packages with generous premium coverage
• $500 per month credit for waiving medical benefits
• Housing subsidy of $2k per month for those living within walking distance of the office
• Relocation support for those moving to San Jose
• Various wellness benefits covering fitness and mental health
• Daily lunch and dinner in the office
• Unlimited compute budget subject to ROI justification