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Posted a day ago
Design Verification Engineer
DensityAIDesign Verification (DV) Engineer
Perks & benefits
Medical InsuranceHealth InsuranceVisaPaid Leave
Requirements
5+ years verification experience, UVM methodology, SoC/full-chip verification, Emulation testing, Hardware/Software specification analysis
Skills
UVMSOCVerification
About the role
Responsibilities
- Own end-to-end verification for AI accelerator silicon
- Develop testing strategies from IP to SoC-level and emulation
- Use and develop AI-assisted tool flows to accelerate verification timelines
- Own an entire testing domain based on expertise
Requirements
- 5+ years of experience in Block Level, Sub System, or SoC verification
- Experience with CPU Subsystem/IP integration or Emulation testing
- Expertise in DMA/NoC Verification or Multi-SoC/Die to Die protocol verification
- Proven record of end-to-end pre-silicon verification ownership
- Well-versed in UVM methodology and testbench architecture
- Strong ability to analyze hardware and software specifications
Preferred Qualifications
- Experience with RISC-V
- Formal verification expertise
- Experience with emulation platforms like Palladium or Veloce
- Post-silicon bring-up experience
About the Company
DensityAI focuses on developing advanced AI accelerator silicon, driving programs from first silicon through scale-out.
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DensityAI · Mountain View
