Design Verification Engineer

Responsibilities

• Develop and implement verification strategies, detailed tests, and coverage plans based on micro-architecture.
• Create verification methodologies and reusable environments, including components such as stimulus, checkers, assertions, and coverage.
• Implement tests, manage regressions, gather coverage, and debug test failures.
• Collaborate with cross-functional teams including architecture, RTL design, physical design, firmware, and validation.
• Analyze and debug complex issues across simulation, emulation, and silicon bring-up phases.
• Continuously enhance verification infrastructure and flows to improve efficiency and quality.
• Work with architects, designers, post-silicon, and software engineers to ensure high-quality silicon design.

Requirements

• 3+ years of Design Verification experience.
• Deep knowledge of SystemVerilog testbench, DPI, and UVM.
• Proficiency in scripting languages such as Python or Perl.
• Experience developing scalable and portable testbenches and components.
• Strong debugging and problem-solving skills.
• Excellent programming skills and knowledge of software engineering practices, including object-oriented design.
• Experience with verification tools such as simulators, waveform viewers, and coverage collection.

Preferred Qualifications

• Knowledge of pipelined processor architecture.
• BS or MS in Computer Science or Electrical Engineering.

About the Company

Cerebras Systems builds the world's largest AI chip, 56 times larger than GPUs. Our novel wafer-scale architecture provides the AI compute power of dozens of GPUs on a single chip, delivering industry-leading training and inference speeds. Cerebras empowers machine learning users to run large-scale ML applications effortlessly, transforming the user experience for top model labs and global enterprises.