Design Verification Engineer

Responsibilities

• Perform functional logic verification at block, subsystem, and full chip levels
• Define and develop scalable, reusable verification plans, test benches, and environments
• Execute verification plans and run emulation and system simulation models to analyze power, performance, and bugs
• Replicate, root cause, and debug issues in the pre-silicon environment
• Collaborate with Architects, RTL developers, and physical design teams to improve verification of complex features
• Document test plans and drive technical reviews with design and architecture teams
• Incorporate security activities within test plans, including regression and debug tests
• Maintain and improve existing functional verification infrastructure and methodologies
• Integrate learnings from post-silicon validation to improve future pre-silicon development

Requirements

• BS, MS, or PhD in Electrical or Computer Science Engineering or a related field
• 6+ years of technical experience in Pre-Silicon Validation/Verification
• Extensive experience with OVM/UVM and SystemVerilog
• Proficiency in constrained random verification methodologies

About the Company

Altera is a leading FPGA company that delivers programmable hardware, software, and development tools to drive innovation from cloud to edge. Our broad portfolio includes FPGAs, CPLDs, IP, SmartNICs, IPUs, and System on Modules, helping to accelerate programmable compute in AI, networking, automotive, and aerospace domains.